Apple sucht einen Frontend-STA Engineer für Cellular SoCs in München. In dieser Rolle sind Sie für die Entwicklung von Constraints sowie für Design- und Timing-Analysen verantwortlich. Sie arbeiten eng mit RTL-Designern, Physical Designern und anderen Integrationsteams zusammen, um innovative Designs zu realisieren und fortschrittliche Technologien zu nutzen. Die Position erfordert Erfahrung in der Constraint-Entwicklung, -Analyse und -Debugging sowie ein gutes Verständnis von hierarchischen Designansätzen und Timing-Konvergenz. Wenn Sie eine Leidenschaft für Innovation und eine starke technische Expertise haben, bietet diese Position die Möglichkeit, einen bedeutenden Beitrag zu Apples Hardwareprodukten zu leisten.
Summary
Posted: May 10, 2024
Role Number:
200527727
Imagine what you could do here. At Apple, new insights quickly translate into extraordinary products, services, and customer experiences. Bring your passion and dedication to our team, and there's no limit to what you can achieve. Join our dynamic team of amazing people, and work with inspiring, innovative technologies. The individuals here have reinvented entire industries with all Apple Hardware products. We extend the same passion for innovation that drives our products to our practices, strengthening our dedication to leaving the world better than we found it. As a Frontend-STA engineer, you'll be a vital member of the Cellular SoC Integration team in Munich, Germany, serving as the key contact for constraints development and design and timing analysis. Collaborating with RTL designers, Physical designers, and other integration teams, you will contribute to exciting designs and cutting-edge technology nodes.
Description
You will spearhead constraint development, including deliveries for synthesis, PnR, and sign-off STA. Working at both partition and SoC levels, you will verify results post-synthesis for all STA modes. As a liaison between digital design, mixed-signal design (.lib definition), and physical design, you will ensure sign-off quality of timing constraints based on stakeholder requirements. You'll also collaborate closely with digital designers to understand design intent and clock structure to optimize power, performance, and area, while partnering with CAD and PD teams to continuously improve development flows.
Key Qualifications
- Hands-on experience on multiple projects with constraint development, -analysis, and -debugging.
- Experience with industry-standard tools for STA, e.g. PrimeTime or Tempus.
- Good understanding of hierarchical design approaches, top-down design, timing budgeting as well as timing and physical convergence.
- Proficient in day-to-day usage of scripting languages (TCL, Perl, shell), Linux, and revision control systems (e.g. PerForce)
- Very good understanding of Verilog and the ability to analyze RTL/Netlist designs
- Experience with SoC practices such as multiple voltage and clock domains, integration of mixed-signal IPs, and power optimizations would be a huge plus
- Experience with synthesis, logic equivalence, or ECO techniques would be a plus
- Good communication skills and the ability to find effective technical solutions between RTL-Design and Physical-Design teams
English language proficiency is required for this position
Education & Experience
A bachelor's or Master's Degree in Electrical Engineering, Computer Science/Software Engineering or equivalent is a requirement. Apple is an equal-opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Apple is committed to working with and providing reasonable accommodation to applicants with physical and mental disabilities.
Additional Requirements