Gestalte deine Karriere als Research Assistant (f/m/d) bei Karlsruher Institut für Technologie in Eggenstein-Leopoldshafen

Organisationseinheit

Institut für Technische Informatik (ITEC)

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Since many years, the Chair for Embedded Systems works internationally successful in the areas of computer engineering, such as smart embedded systems. Many interesting and open problems in these areas need to be addressed to successfully deploy such systems in modern application domains. As an example, the most urgent questions about memory architectures in real-time systems are highlighted in the following.

Embedded systems and real-time systems are ubiquitous in our everyday life, e.g., in safety-critical domains such as automotive or avionics. However, embedded systems usually have limited energy, computing power, and memory/storage space. Hardware accelerators and revolutionary memory hierarchies are very promising candidates to tackle these challenges. On the memory side, the emerging byte-addressable non-volatile memories (referred to as NVMs for short), such as Phase Change Memory (PCM), Spin-Transfer Torque RAM (STT-RAM) and Resistive RAM (ReRAM), feature low leakage power, high density, and low unit costs. NVMs are hence interesting alternatives to replace (i) DRAM as main memory and/or (ii) hard disks and flash as storage. On the hardware accelerator side, application-specific and reconfigurable accelerators have proven their benefits with regards to computing throughput, energy efficiency, etc. However, in order to deploy NVM and hardware accelerators in embedded real-time systems, it is crucial to be able to determine a safe upper bound for their execution time. The correctness of a real-time system does not only depend on the correctness of its calculations, but also on the non-functional requirement of adhering to timing deadlines. Failing to meet a deadline may lead to severe malfunctions or even threaten life, therefore timing analysis is needed to determine its worst-case execution time (WCET).

In the scope of this research project, we want to investigate the challenges of WCET analysis and WCET optimizations for systems that use hardware accelerators and NVM main memory. Existing WCET analysis tools focus on software executing on simple processors (without accelerators) and DRAM main memory (no NVM). The challenges regarding the accelerators is their inherent parallelism that needs to be modeled in order to provide a safe upper bound for their execution time. As this will not be possible in all cases, a HW/WCET co-design appears promising, i.e., designing an accelerator in an analyzable way, potentially trading peak performance vs. a better timing guarantee. Regarding NVM memory, NVM-specific maintenance operations need to be considered for timing analysis. For instance, to avoid wearing out the NVM cells too fast, wear-levelling approaches are typically used to redistribute memory accesses across the storage, which involves copying data, which costs time. In best case, such maintenance operations can be ‘hidden’, i.e. they are executed without affecting the performance of CPU and accelerators. Specific wear-leveling algorithms and specific hardware accelerators for wear leveling will be advantageous for those cases. Additionally, we want to investigate: WCET analysis for systems with NVM memory, optimizations for applications running on those systems (e.g. trading execution time with data retention time), hardware implementations for wear-levelling approaches, FPGA-based runtime reconfiguration to switch between system services (wear levelling) and application-specific accelerators, WCET analysis of hardware accelerators, in-/near-memory computing approaches, etc.

Eintrittstermin

as soon as possible

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